Technical Field
Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to processors to process packed data.
Background Information
Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements packed within a register or memory location as packed data, vector data, or SIMD data. Representatively, the bits of the register may be logically divided into a sequence of data elements. For example, a 128-bit wide packed data register may have sixteen 8-bit data elements, eight 16-bit data elements, four 32-bit data elements, or two 64-bit data elements. Each of the data elements may represent a separate individual piece of data (e.g., a pixel color, a component of a complex number, etc.), which may be operated upon separately and/or independently of the others. The processor may have parallel execution hardware, responsive to the packed data instruction, to operate on the data elements concurrently and/or in parallel.